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參數(shù)資料
| 型號： | MT24D836M |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 8Meg x 36 Parity DRAM SIMMs(8M x 36奇偶校驗動態(tài)RAM（單列直插存儲器模塊）) |
| 中文描述： | 8Meg × 36平價的DRAM的SIMM（8米× 36奇偶校驗動態(tài)隨機存儲器（單列直插存儲器模塊）） |
| 文件頁數(shù)： | 8/17頁 |
| 文件大小： | 308K |
| 代理商： | MT24D836M |
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
8
4, 8 MEG x 36
PARITY DRAM SIMMs
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
V
CC
= 4.5V, DC bias = 2.4V at 15mV RMS).
3. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured.
6. An initial pause of 100
μ
s is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
t
REF refresh
requirement is exceeded.
7. AC characteristics assume
t
T = 5ns.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
10. If CAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from the
last valid READ cycle.
12. Measured with a load equivalent to two TTL gates
and 100pF, V
OL
= 0.8V and V
OH
= 2V.
13. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
t
CP.
14. The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC must
always be met.
15. The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively by
t
AA (
t
RAC and
t
CAC no longer applied). With or
without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC
must always be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles.
19. OE# is tied permanently LOW; LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted.
20. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21. The 3ns minimum is a parameter guaranteed by
design.
22. Column address changed once each cycle.
23. 16MB module values will be half of those shown.
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