參數(shù)資料
型號: MSM7731-02
廠商: OKI SEMICONDUCTOR CO., LTD.
元件分類: Codec
英文描述: Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free
中文描述: 雙回聲消除器
文件頁數(shù): 33/43頁
文件大?。?/td> 247K
代理商: MSM7731-02
33/43
Semiconductor
MSM7731-01
(5) CR4 (Line echo canceler settings)
B7.......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation)
This is the "through mode" control bit for the line echo canceler. In the "through
mode", RinL and SinL data is output directly to RoutL and SoutL respectively.
Coefficients are not reset.
This bit is internally ORed with the LTHR pin.
B6, B5 ... Reserved bits
B4.......... Howling detector control
This bit controls the function to detect and cancel the howling that occurs in an
acoustic system such as a handsfree communication system.
This bit is internally ORed with the
LHD
pin.
B3.......... Center clip control
When the SoutL output of the line echo canceler is –57 dBm0 or less, the center
clip function forcibly sets it to the minimum positive value.
B2.......... Coefficient update control
This bit selects whether the adaptive FIR filter (AFR) coefficients for the line
echo canceler will be updated.
This bit is internally ORed with the LHLD pin.
B1.......... Attenuator control
This bit turns ON or OFF the ATT function to prevent howling by means of
attenuators (ATTsL, ATTrL) provided in the RinL input and SoutL output of
the line echo canceler.
If input is only to RinL, the ATT for SoutL (ATTsL) is activated. If input is only
to SinL, or if there is input to both SinL and RinL, the ATT for RinL input
(ATTrL) is activated. The ATT value of each attenuator is approximately 6 dB.
This bit is internally ORed with the
LATT
pin.
B0.......... Gain controller
This bit turns ON or OFF the gain control function to control the RinL input
level and prevent howling by means of a gain controller (GainL) provided in the
RinL input of the line echo canceler.
The gain controller adjusts the RIN input level when it is –10 dBm0 or above,
and it has the control range of 0 to –8.5 dB.
This bit is internally ORed with the
LGC
pin.
Modification of initial values is inhibited
1: OFF,
0: ON
1: ON,
0: OFF
1: fixed coefficients,
0: updated coefficients
1: ATT OFF,
0: ATT ON
1: GC OFF,
0: GC ON
B7
LTHR
0
B6
0
B5
0
B4
LHD
0
B3
LCLP
0
B2
LHLD
0
B1
LATT
0
B0
LGC
0
CR4
Initial value
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