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Semiconductor
MSM7731-01
(2) CR1
B7.......... Internal data memory write control
In internal data memory, the data set in CR8 (D15 to D8) and CR9 (D7 to D0) is
written to the memory address set in CR6 (A15 to A8) and CR7 (A7 to A0).
Writing is possible only during the initial mode.
For further details, refer to the internal data memory access method.
B6, B5, B4, B3 .. Reserved bits
B2.......... Echo canceler I/O PAD control
This bit controls the attenuators (LPADL/A) provided in the SinL/A inputs
and the amplifiers (GPADL/A) provided in the SoutL/A outptus of the echo
canceler. Levels are set by the CR10 register. Use this bit when the echo return
loss (value of returned echo) is amplified. This bit is internally ORed with the
GLPADTHR
pin.
B1.......... Slope filter control
0: normal mode (slope filter operation),
This bit controls operation of the transmit slope filter. In the "through mode",
the filter is halted and data is output directly. This bit is internally ORed with
the SLPTHR pin.
B0.......... Noise canceler control 0: normal mode (noise canceler operation), 1: "through mode"
This bit controls operation of the noise canceler. In the "through mode", the
noise canceler is halted and data is output directly. This bit is internally ORed
with the NCTHR pin. If this bit is changed to the normal mode, approximately
20 ms of data dropout will occur.
0: write inhibited,
1: write
Modification of initial values is inhibited
0: "through mode",
1: normal mode
1: "through mode"
B7
DMWR
0
B6
—
0
B5
—
0
B4
—
0
B3
—
0
B2
GLPADTHR
0
B1
SLPTHR
0
B0
NCTHR
0
CR1
Initial value