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參數(shù)資料
| 型號： | MSM63P180-NGS-BK |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 236K |
| 代理商： | MSM63P180-NGS-BK |
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Semiconductor
MSM63P180
11/35
Table 2 shows the secondary functions of each pin of the MSM63P180.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin
Type
Description
External
Interrupt
PB.0/INT0
108
PB.1/INT0
107
PB.2/INT0
106
PB.3/INT0
105
PC.0/INT1
I
PC.1/INT1
103
PC.2/INT1
102
PC.3/INT1
101
PE.3/INT2
93
PF.0/INT3
92
PF.1/INT3
91
PF.2/INT3
90
PF.3/INT3
89
P0.0/INT5
154
P0.1/INT5
153
P0.2/INT5
152
P0.3/INT5
151
P1.0/INT5
150
P1.1/INT5
149
P1.2/INT5
148
P1.3/INT5
147
P1.0/TBCAP0
150
I
P1.1/TBCAP1
149
PB.0/TM0CAP
108
I
PB.1/TM1CAP
107
I
External 0 interrupt input pins.
The change of input signal level causes an interrupt to occur.
The Port B Interrupt Enable register (PBIE) enables or disables
an interrupt for each bit.
External 2 interrupt input pin.
The change of input signal level causes an interrupt to occur.
External 3 interrupt input pins.
The change of input signal level causes an interrupt to occur.
The Port F Interrupt Enable register (PFIE) enables or disables
an interrupt for each bit.
External 5 interrupt input pins.
The change of input signal level causes an interrupt to occur.
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
Enable register (P1IE) enable or disable an interrupt for each bit.
Time base counter capture trigger input pins
Timer 0 capture trigger input pin
Timer 1 capture trigger input pin
I
104
Capture
I
External 1 interrupt input pins.
The change of input signal level causes an interrupt to occur.
The Port C Interrupt Enable register (PCIE) enables or disables
an interrupt for each bit.
P8.3/INT4
117
External 4 interrupt input pin.
The change of input signal level causes an interrupt to occur.
I
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