參數(shù)資料
型號(hào)： MSM548262-80JS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 262,144-Word x 8-Bit Multiport DRAM
中文描述： 262,144字× 8位多端口內(nèi)存
文件頁數(shù)： 9/37頁
文件大?。?/td> 464K
代理商： MSM548262-80JS
Semiconductor
MSM548262
9/37
Notes:
1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage
to the device.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate.
4. These parameters depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200
m
s is required after power up followed by any 8
RAS
cycles
(
TRG
= "high") and any 8 SC cycles before proper device operation is achieved.
In the case of using an internal refresh counter, a minimum of 8
CAS
before
RAS
cycles instead of 8
RAS
cycles are required.
6. AC measurements assume t
T
= 5 ns.
7. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between V
IH
and V
IL
.
8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.
DOUT reference levels : V
OH
/V
OL
= 2.0 V/0.8 V.
9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
DOUT
reference levels : V
OH
/V
OL
= 2.0 V/0.8 V.
10. t
OFF
(Max.), t
OEZ
(Max.), t
SDZ
(Max.) and t
SEZ
(Max.) define the time at which the
outputs achieve the open circuit condition, and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
11. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
12. These parameters are referenced to
CAS
leading edge of early write cycles, and to
WE
leading edge in
TRG
controlled write cycles and read modify write cycles.
13. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters.
They are included in the data sheet as electrical characteristics only.
If t
WCS
≥
t
WCS
(Min.), the cycle is an early write cycle, and the data out pin will
remain open circuit throughout the entire cycle; If t
RWD
≥
t
RWD
(Min.), t
CWD
≥
t
CWD
(Min.) and t
AWD
≥
t
AWD
(Min.), the cycle is a read modify write cycle, and the data
out will contain data read from the selected cell; If neither of the above sets of
conditions are satisfied, the condition of the data out is indeterminate.
14. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only: If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then access time is controlled by t
CAC
.
15. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RAD
(Max.) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(Max.) limit, then access time is controlled by t
AA
.
16. Input levels at the AC testing are 3.0 V/0 V.
17. Address (A0 - A8) may be changed two times or less while
RAS
= V
IL
.
18. Address (A0 - A8) may be changed once or less while
CAS
= V
IH
and
RAS
= V
IL
.
19. This is guaranteed by design. (t
SOH
/t
COH
= t
SCA
/t
CAC
- output transition time)
This parameter is not 100% tested.
相關(guān)PDF資料
PDF描述
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