- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378013 > MSM548262-80JS (OKI SEMICONDUCTOR CO., LTD.) 262,144-Word x 8-Bit Multiport DRAM PDF資料下載
參數(shù)資料
| 型號： | MSM548262-80JS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word x 8-Bit Multiport DRAM |
| 中文描述： | 262,144字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 34/37頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MSM548262-80JS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁
Semiconductor
MSM548262
34/37
Read Transfer:
RAS
falling edge ---
CAS
=
WE
= "H",
TRG
= DSF = "L"
Read transfer consists of loading a selected row of data from the RAM into the SAM register. A
read transfer is invoked by holding
CAS
"high",
TRG
"low",
WE
"high", and DSF "low" at the
falling edge of
RAS
. The row address selected at the falling edge of
RAS
determines the RAM row
to be transferred into the SAM. The transfer cycle is completed at the rising edge of
TRG
. When
the transfer is completed, the SAM port is set into the output mode. In a read/real time read
transfer cycle, the transfer of a new row of data is completed at the rising edge of
TRG
, and this
data becomes valid on the SDQ lines after the specified access time t
SCA
from the rising edge of
the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the
column address selected at the falling edge of
CAS
. In a read transfer cycle (which is preceded
by a write transfer cycle), SC clock must be held at a constant V
IL
or V
IH
after the SC high time
has been satisfied. A rising edge of the SC clock must not occur until after the specified delay t
TSD
from the rising edge of
TRG
.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SQD lines until the
TRG
signal goes "high", and the serial access time
t
SCA
for the following serial clock is satisfied. This feature allows for the first bit of the new row
of data to appear on the serial output as soon as the last bit of the previous row has been strobed
without any timing loss. To make this continuous data flow possible, the rising edge of
TRG
must
be synchronized with
RAS
,
CAS
, and the subsequent rising edge of SC (t
RTH
, t
CTH
, and t
TSL
/t
TSD
must be satisfied).
Masked Write Transfer:
RAS
falling edge ---
CAS
= "H",
TRG
=
WE
= DSF = "L"
Write transfer cycle consists of loading the content of the SAM register into a selected row of the
RAM. This write transfer is the same as a mask write operation in RAM.
If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer
operation (all DQ pins "low" at falling edge of
RAS
) must precede the write transfer cycles. A
masked write transfer is invoked by holding
CAS
"high",
TRG
"low",
WE
"low" and DSF "low"
at the falling edge of
RAS
. The row address selected at the falling edge of
RAS
determines the
RAM row address into which the data will be transferred. The column address selected at the
falling edge of
CAS
determines the start address of the serial pointer of the SAM. After the write
transfer is completed, the SDQ lines are set in the input mode so that serial data synchronized
with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the
RAS
cycle of the preceding write transfer is completed. Consequently,
the SC clock must be held at a constant V
IL
or V
IH
during the
RAS
cycle. A rising edge of the SC
clock is only allowed after the specified delay t
CSD
from the falling edge of the
CAS
, at which time
a new row of data can be written in the serial register.
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the
other address of RAM by write transfer cycle. However, the address to write data must be the
same as that of the read transfer cycle (row address AX8).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM548262-80TS-K | 262,144-Word x 8-Bit Multiport DRAM |
| MSM548262 | 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM) |
| MSM548263 | 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM) |
| MSM548512L-XXGS-K | 524,288-Word X 8-Bit High-Speed PSRAM |
| MSM548512L | 524,288-Word X 8-Bit High-Speed PSRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM548262-JS70 | 制造商:ROHM Semiconductor 功能描述: |
| MSM548263-60JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM548263-60TS-K | 制造商:OK International 功能描述: |
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。