- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378013 > MSM548262-80JS (OKI SEMICONDUCTOR CO., LTD.) 262,144-Word x 8-Bit Multiport DRAM PDF資料下載
參數(shù)資料
| 型號： | MSM548262-80JS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word x 8-Bit Multiport DRAM |
| 中文描述： | 262,144字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 27/37頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MSM548262-80JS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
Semiconductor
MSM548262
27/37
PIN FUNCTIONS
Address Input: A0 - A8
The 18 address bits decode 8 bits of the 2,097,152 locations in the MSM548262 memory array. The
address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address
bits are latched at the falling edge of
RAS
. The following 9 column address bits are latched at the
falling edge of
CAS
.
Row Address Strobe:
RAS
RAS
is a basic RAM control signal. The RAM port is in standby mode when the
RAS
level is
"high". As the standard DRAM’s
RAS
signal function,
RAS
is the control input that latches the
row address bits, and a random access cycle begins at the falling edge of
RAS
.
In addition to the conventional
RAS
signal function, the level of the input signals
CAS
,
TRG
,
WE
and DSF at the falling edge of
RAS
, determines the MSM548262 operation mode.
Column Address Strobe:
CAS
As the standard DRAM’s
CAS
signal function,
CAS
is the control input signal that latches the
column address input and the state of the special function input DSF to select in conjunction with
the
RAS
control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of
RAS
.
CAS
also acts as a RAM port output enable signal.
Data Transfer/Output Enable:
TRG
TRG
is also a control input signal having multiple functions. As the standard DRAM’s
OE
signal
function,
TRG
is used as an output enable control when
TRG
is "high" at the falling edge of
RAS
.
In addition to the conventional
OE
signal function, a data transfer operation is started between
the RAM port and the SAM port when
TRG
is "low" at the falling edge of
RAS
.
Write Per Bit/Write Enable:
WE
WE
is a control input signal having multiple functions. As the standard DRAM’s
WE
signal
function, this is used to write data into the memory on the RAM port when
WE
is "high" at the
falling edge of
RAS
.
In addition to the conventional
WE
signal function, the
WE
determines the write-per-bit
function, when
WE
is "low" at the falling edge of
RAS
during RAM port operations.
The
WE
also determines the direction of data transfer between the RAM and SAM. When the
WE
is "high" at the falling edge of
RAS
, the data is transferred from RAM to SAM (read transfer).
When the
WE
is "low" at the falling edge of
RAS
, the data is transferred SAM to RAM (write
transfer).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM548262-80TS-K | 262,144-Word x 8-Bit Multiport DRAM |
| MSM548262 | 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM) |
| MSM548263 | 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM) |
| MSM548512L-XXGS-K | 524,288-Word X 8-Bit High-Speed PSRAM |
| MSM548512L | 524,288-Word X 8-Bit High-Speed PSRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM548262-JS70 | 制造商:ROHM Semiconductor 功能描述: |
| MSM548263-60JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM548263-60TS-K | 制造商:OK International 功能描述: |
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。