參數(shù)資料
型號: MSC8144ESVT1000B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 60/80頁
文件大?。?/td> 1251K
代理商: MSC8144ESVT1000B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
63
2.6.14
JTAG Signals
Figure 38 Shows the Test Clock Input Timing Diagram
Figure 39 Shows the boundary scan (JTAG) timing diagram.
Table 50. JTAG Timing
Characteristics
Symbol
All frequencies
Unit
Min
Max
TCK cycle time
tTCKX
36.0
ns
TCK clock high phase measured at VM = 1.6 V
tTCKH
15.0
ns
TCK rise and fall times
tTCKR
—3.0
ns
Boundary scan input data setup time
tBSVKH
0.0
ns
Boundary scan input data hold time
tBSXKH
15.0
ns
TCK fall to output data valid
tTCKHOV
20.0
ns
TCK fall to output high impedance
tTCKHOZ
24.0
ns
TMS, TDI data setup time
tTDIVKH
0.0
ns
TMS, TDI data hold time
tTDIXKH
5.0
ns
TCK fall to TDO data valid
tTDOHOV
10.0
ns
TCK fall to TDO high impedance
tTDOHOZ
12.0
ns
TRST assert time
tTRST
100.0
ns
Note:
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 38. Test Clock Input Timing
Figure 39. Boundary Scan (JTAG) Timing
TCK
(Input)
VM
tTCKX
tTCKH
tTCKR
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Input Data Valid
Output Data Valid
tBSXKH
tBSVKH
tTCKHOV
tTCKHOZ
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