參數(shù)資料
型號: MSC8144ESVT1000B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 51/80頁
文件大?。?/td> 1251K
代理商: MSC8144ESVT1000B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
55
2.6.10.2
MII Transmit AC Timing Specifications
Table 41 provides the MII transmit AC timing specifications.
Figure 25 shows the MII transmit AC timing diagram.
2.6.10.3
MII Receive AC Timing Specifications
Table 42 provides the MII receive AC timing specifications.
Figure 24. MII Management Interface Timing
Table 41. MII Transmit AC Timing Specifications
Parameter/Condition
Symbol 1
Min
Max
Unit
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
025
ns
Notes:
1.
Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2.
Program GCR4 as 0x00030CC3.
Figure 25. MII Transmit AC Timing
Table 42. MII Receive AC Timing Specifications
Parameter/Condition
Symbol 1
Min
Max
Unit
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
2—
ns
Notes:
1.
Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2.
Program GCR4 as 0x00030CC3.
ETHMDC
ETHMDIO
(Input)
(Output)
tMDC
tMDDXKH
tMDDVKH
tMDKHDX
TX_CLK
TXD[3:0]
tMTKHDX
TX_EN
TX_ER
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