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參數(shù)資料
| 型號(hào)： | MSC8126TMP6400 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 400 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 35/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126TMP6400 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Hardware Design Considerations
Freescale Semiconductor
40
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN
can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up
VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and
then VDD/VCCSYN.
Note:
This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply through the
device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
Never allow VDD to exceed VDDH + 0.8V.
Design the VDDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial VDDH level of VDD – 0.8 V before it is enabled.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374
for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)
provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
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