參數(shù)資料
型號(hào)： MSC1211Y2PAGTG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 71/111頁(yè)
文件大?。?/td> 1102K
代理商： MSC1211Y2PAGTG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
62
I2C Start (I2CSTART) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Eh
80h
I2CSTART
I2C Start. Write-only. When any value is written to this register, the I2C system is reset; that is, the counters
bits 70
and state machines will go back to the initial state. So, in multi-master mode when arbitration is lost, then the I2C
should be reset so that the counters and finite state machines (FSMs) are brought back to the idle state.
SPI Buffer Start Address (SPISTART)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Eh
1
80h
SPISTART
SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a circular FIFO
bits 60
that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified
in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters.
SPITP
SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next byte will
bits 60
be written into the byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data
register unless that would make it equal to the SPI Receive pointer.
SPI Buffer End Address (SPIEND)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Fh
1
80h
SPIEND
SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer that
bits 60
is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address.
SPIRP
SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the next byte
bits 60
to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero.
Port 2 (P2)
7
6
5
4
3
2
1
0
Reset Value
SFR A0h
FFh
P2
Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port.
bits 70
During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as
general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).
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MSC1211Y4PAGTG4 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
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