參數(shù)資料
型號: MSC1211Y2PAGTG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 57/111頁
文件大?。?/td> 1102K
代理商: MSC1211Y2PAGTG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
5
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz,
and VREF ≡ (REF IN+) (REF IN) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
MSC1211/12/13/14
PARAMETER
UNITS
MAX
TYP
MIN
CONDITIONS
Analog Power-Supply Requirements
Analog Power-Supply Voltage
AVDD
4.75
5
5.25
V
Analog Off Current(8)
Analog OFF, PDCON = 48h
< 1
nA
PGA = 1, Buffer OFF
200
A
Analog
ADC Current (IADC)
PGA = 128, Buffer OFF
500
A
Analog
Power-Supply
ADC Current (IADC)
PGA = 1, Buffer ON
240
A
Power-Supply
Current
PGA = 128, Buffer ON
850
A
Current
VDAC Current (IVDAC)
Excluding Load Current, External Reference
250
A
VREF Supply Current
(IVREF)
ADC ON, VDAC OFF
250
A
(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M/64).
(2) Calibration can minimize these errors.
(3) The self gain calibration cannot have a REF IN+ of more than AVDD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4) VOUT is change in digital result.
(5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14).
(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
(7) Ensured by design and characterization; not production tested.
(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz,
and VREF ≡ (REF IN+) (REF IN) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
MSC1211/12/13/14
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Inputs (AIN0AIN7, AINCOM)
Analog Input Range
Buffer OFF
AGND 0.1
AVDD + 0.1
V
Analog Input Range
Buffer ON
AGND + 50mV
AVDD 1.5
V
Full-Scale Input Voltage Range
(AIN+) (AIN)
±VREF/PGA
V
Differential Input Impedance
Buffer OFF
7/PGA(1)
M
Input Current
Buffer ON
0.5
nA
Fast Settling Filter
3dB
0.469
fDATA
Bandwidth
Sinc2 Filter
3dB
0.318
fDATA
Bandwidth
Sinc3 Filter
3dB
0.262
fDATA
Programmable Gain Amplifier
User-Selectable Gain Range
1
128
Input Capacitance
Buffer ON
9
pF
Input Leakage Current
Multiplexer Channel OFF, T = +25
°C
0.5
pA
Burnout Current Sources
Sensor Input Open Circuit
±2
A
(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M/64).
(2) Calibration can minimize these errors.
(3) The gain calibration cannot have a REF IN+ of more than AVDD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4) VOUT is change in digital result.
(5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14).
(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
(7) Ensured by design and characterization; not production tested.
(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
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