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參數(shù)資料
| 型號： | MR82C37A/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 430K |
| 代理商： | MR82C37A/B |
13
FN2967.2
March 20, 2006
82C37A
received, addresses and control signals are generated by
the DMA controller to accomplish the DMA transfers. Data is
transferred directly from the I/O device to memory (or vice
versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-memory or memory-to-I/O data
transfers.
FIGURE 6. APPLICATION FOR DMA SYSTEM
MEMR
MEMW
IOR
IOW
MEMCS
MEMR
MEMW
MEMORY
47k
VCC
ADDRESS BUS
DATA BUS
VCC
DATA BUS
80C88
WR
RD
M/IO
HRQ
HLDA
AX
ALE
AD0
AD7
MN/MX
CLK
82C84A
OR
82C85
HLDA
MEMCS
STB
82C82
OE
DECODER
ADDRESS BUS
STB
82C82
OE
A0-7
CS
CLK
EOP
HLDA
IOR
DACK
ADSTB
AEN
DB0-7
IOW
MEMR
MEMW
HRQ
DREQ0
82C37A
IOR
IOW
VCC
CS
DREQ
I/O
DEVICE
NOTE: The address lines need pull-up resistors.
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