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參數(shù)資料
| 型號： | MR82C37A/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 430K |
| 代理商： | MR82C37A/B |
2
FN2967.2
March 20, 2006
82C37A
Block Diagram
Pinouts
82C37A (PDIP/CERDIP)
TOP VIEW
82C37A (CLCC/PLCC)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
(GND) VSS
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
A7
A6
A5
A4
EOP
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
DB4
DACK0
DACK1
DB5
DB6
DB7
14
13
12
11
10
9
8
7
17
16
15
2
5
30
35
39
38
37
36
33
34
32
31
29
4
6
3
1
40
41
42
43
44
28
27
26
25
24
23
22
21
20
19
18
CS
DACK2
NC
CLK
HRQ
NC
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
NC
DB4
READ
Y
NC
A7
A6
A5
MEMW
A4
EOP
D
A
CK3
DREQ3
DREQ2
DREQ1
DREQ0
GND
DB5
D
A
CK1
DB7
D
A
CK0
DB6
MEMR
ADSTB
AEN
IO
W
RESET
HLDA
IOR
A4 - A7
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0 -
HLDA
HRQ
DACK0 -
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DACK3
4
DREQ3
4
COMMAND
(8)
MASK
(4)
REQUEST
(4)
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
INTERNAL DATA BUS
DECREMENTOR
COUNT REG (16)
TEMP WORD
INC/DECREMENTOR
REG (16)
TEMP ADDRESS
BUFFER
IO
16-BIT BUS
READ BUFFER
ADDRESS
BASE
(16)
WORD
BASE
COUNT
(16)
READ WRITE BUFFER
ADDRESS
CURRENT
(16)
WORD
CURRENT
COUNT
(16)
16-BIT BUS
BUFFER
WRITE
BUFFER
READ
A8
-
A15
BUFFER
OUTPUT
CONTROL
COMMAND
D0 - D1
A0 - A3
BUFFER
IO
DB0
-
DB7
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