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參數(shù)資料
| 型號： | MR82C37A/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MR82C37A/B |
11
FN2967.2
March 20, 2006
82C37A
edge. Status Bits 4-7 are cleared upon RESET or Master
Clear.
Temporary Register - The Temporary register is used to
hold data during memory-to-memory transfers. Following the
completion of the transfers, the last byte moved can be read
by the microprocessor. The Temporary register always
contains the last byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset or Master
Clear.
Software Commands
There are special software commands which can be
executed by reading or writing to the 82C37A. These
commands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop - This command is executed
prior to writing or reading new address or word count
information to the 82C37A. This command initializes the flip-
flop to a known state (low byte first) so that subsequent
accesses to register contents by the microprocessor will
address upper and lower bytes in the correct sequence.
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
Master Clear - This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an
internal two-bit counter has been included to select Mode
registers during read operation. To read the Mode registers,
first execute the Clear Mode Register Counter command,
then do consecutive reads until the desired channel is read.
Read order is channel 0 first, channel 3 last. The lower two
bits on all Mode registers will read as ones.
Status Register
76543210
BIT NUMBER
1 Channel 0 has reached TC
1 Channel 1 has reached TC
1 Channel 2 has reached TC
1 Channel 3 has reached TC
1 Channel 0 request
1 Channel 1 request
1 Channel 2 request
1 Channel 3 request
OPERATION
A3A2A1A0
IOR
IOW
Read Status Register
100001
Write Command Register
100010
Read Request Register
100101
Write Request Register
100110
Read Command Register
101001
Write Single Mask Bit
101010
Read Mode Register
101101
Write Mode Register
101110
Set First/Last F/F
110001
Clear First/Last F/F
110010
Read Temporary Register
110101
Master Clear
110110
Clear Mode Reg. Counter
111001
Clear Mask Register
111010
Read All Mask Bits
111101
Write All Mask Bits
111110
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES
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