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| 型號(hào)： | MR80C52XXX-12 |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 8/336頁(yè) |
| 文件大小： | 8801K |
| 代理商： | MR80C52XXX-12 |
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105
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
15.6.1
Input Capture trigger source
The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B).
Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared
after the change.
The Input Capture pin (ICPn) IS sampled using the same technique as for the Tn pin (see Figure 16-1 on page
124). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise
canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generating mode
that uses ICRn to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICPn pin.
15.6.2
Noise canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control
Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
15.6.3
Using the Input Capture unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a
change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is
used).
15.6.4
Using the Input Capture unit as TCNT1 Retrigger Input
TCNT1 counts from BOTTOM to TOP. The TOP value can be a fixed value, ICR1, or OCR1A. When enabled the
Retrigger Input forces to reach the TOP value. It means that ICF1 output is ored with the TOP signal.
15.7
Output Compare units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals
OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock
cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx Flag
is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software
by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the Waveform Generating mode (WGMn3:0) bits and Compare Output mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MF180C51T-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| MR80C32-12:D | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C32E-36:D | 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52TXXX-16SHXXX:R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C32E-20:R | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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