33
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
8.11
Register description
8.11.1
OSCCAL – Oscillator Calibration Register
Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia-
tions from the oscillator frequency. A pre-programmed calibration value is automatically written to this register
during chip reset, giving the Factory calibrated frequency as specified in
Table 28-1 on page 296. The application
software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM
or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre-
quency in that range, and a setting of 0x7F gives the highest frequency in the range.
8.11.2
PLLCSR – PLL Control and Status Register
Bit 7:3 – Res: Reserved Bits
These bits are reserved and always read as zero.
Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference
clock. If PLL is selected as a system clock source the value for this bit is always 1.
Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLK
PLL for Fast
Peripherals. After the PLL is enabled, it takes about 100ms for the PLL to lock.
Bit
76543210
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/write
R/W
Initial value
Device Specific Calibration Value
Bit
7
6543
210
–
––––
PLLF
PLLE
PLOCK
PLLCSR
Read/write
R
R/W
R
Initial value
0
0000
0
0/1
0