58
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
12.2.5
PCIFR – Pin Change Interrupt Flag Register
Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
Bit 3 - PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT26:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in
SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in
SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in
SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
12.2.6
PCMSK3 – Pin Change Mask Register 3
Bit 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 2:0 – PCINT26:24: Pin Change Enable Mask 26:24
Each PCINT26:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT26:24
is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT23:24 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit
7
6
543
21
0
–
PCIF3
PCIF2
PCIF1
PCIF0
PCIFR
Read/write
RRR
RR
R/W
Initial value
0
Bit
7
65
43
2
1
0
-
PCINT26
PCINT25
PCINT24
PCMSK3
Read/write
R/W
Initial value
0