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參數(shù)資料
| 型號(hào)： | MR80C52CXXX-20 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 135/170頁 |
| 文件大?。?/td> | 25028K |
| 代理商： | MR80C52CXXX-20 |
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22
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
8.4
EEPROM data memory
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 512/1K/2K/4Kbytes
of data EEPROM memory. It is organized as a separate data space, in which single bytes can
be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
8.4.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space. See ”Register Description” on
page 24 for details.
The write access time for the EEPROM is given in Table 8-2 on page 26. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
CC is likely to rise or fall slowly on power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See Section “8.4.2” on page 22 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
8.4.2
Preventing EEPROM corruption
During periods of low V
CC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low V
CC reset Protection circuit can
be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
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