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參數(shù)資料
| 型號： | MR80C52CXXX-20 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 129/170頁 |
| 文件大小： | 25028K |
| 代理商： | MR80C52CXXX-20 |
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214
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
21.3.4
Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 21-5. Data packet format.
21.3.5
Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 21-6 on page 214 shows a typical data transmission. Note that several data bytes can be
transmitted between the SLA+R/W and the STOP condition, depending on the software protocol
implemented by the application software.
Figure 21-6. Typical data transmission.
12
78
9
Data MSB
Data LSB
ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W
Data Byte
STOP, REPEATED
START or Next
Data Byte
12
7
8
9
Data Byte
Data MSB
Data LSB
ACK
SDA
SCL
START
12
7
8
9
Addr MSB
Addr LSB
R/W
ACK
SLA+R/W
STOP
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