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參數(shù)資料
| 型號： | MR80C32-30SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 99/109頁 |
| 文件大小： | 10824K |
| 代理商： | MR80C32-30SCD |
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75
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
11.9.7 TIFR – Timer/Counter Interrupt Flag Register
Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Bit 2 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output
Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output
Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0
Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG
I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is
executed.
The setting of this flag is dependent of the WGM0[2:0] bit setting. See Table 11-8 on page 72 and Table 12-5 on page 98.
Bit
76543210
ICF1
–
OCF1B
OCF1A
TOV1
OCF0B
OCF0A
TOV0
TIFR
Read/Write
R/W
R
R/W
Initial Value
00000000
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