參數(shù)資料
型號: MR80C32-30SCD
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 28/109頁
文件大小: 10824K
代理商: MR80C32-30SCD
273
7593L–AVR–09/12
AT90USB64/128
Figure 23-9. USB device controller endpoint interrupt system.
Processing interrupts are generated when:
Ready to accept IN data(EPINTx, TXINI=1)
Received OUT data(EPINTx, RXOUTI=1)
Received SETUP(EPINTx, RXSTPI=1)
Exception Interrupts are generated when:
Stalled packet(EPINTx, STALLEDI=1)
CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)
Overflow in isochronous mode(EPINTx, OVERFI=1)
Underflow in isochronous mode(EPINTx, UNDERFI=1)
NAK IN sent(EPINTx, NAKINI=1)
NAK OUT sent(EPINTx, NAKOUTI=1)
23.18 Registers
23.18.1
USB device general registers
EPINT
UEINT.X
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
Endpoint 4
Endpoint 5
Endpoint interrupt
Endpoint 6
FLERRE
UEIENX.7
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6
NAKINE
UEIENX.6
NAKOUTI
UEINTX.4
TXSTPE
UEIENX.4
RXSTPI
UEINTX.3
TXOUTE
UEIENX.3
RXOUTI
UEINTX.2
RXOUTE
UEIENX.2
STALLEDI
UEINTX.1
STALLEDE
UEIENX.1
TXINI
UEINTX.0
TXINE
UEIENX.0
Bit
7
65
43
2
1
0
--
-
LSM
RMWKUP
DETACH
UDCON
Read/write
RR
R
R/W
Initial value
00
0
1
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