參數(shù)資料
型號(hào)： MR80C32-30SCD
廠商： TEMIC SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 95/109頁(yè)
文件大?。?/td> 10824K
代理商： MR80C32-30SCD
71
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
These bits control the Output Compare pin (OC0B) behavior. If one or both of COM0B[1:0] bits are set, the OC0B output
overrides the normal port functionality of the I/O pin it is connected to. The Data Direction Register (DDR) bit
corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of COM0B[1:0] bits depend on WGM0[2:0] bit setting. Table 11-5
shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to normal or CTC mode (non-PWM).
Table 11-5.
Compare Output Mode, non-PWM Mode
Table 11-6 shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode.
Table 11-6.
Compare Output Mode, Fast PWM Mode
Note:
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is
ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 65 for more details.
Table 11-7 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
Table 11-7.
Compare Output Mode, Phase Correct PWM Mode
Note:
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is
ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 66 for more details.
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Toggle OC0B on Compare Match
1
0
Clear OC0B on Compare Match
1
Set OC0B on Compare Match
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match, set OC0B at BOTTOM
(non-inverting mode)
1
Set OC0B on Compare Match, clear OC0B at BOTTOM
(inverting mode)
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match
when down-counting.
1
Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match
when down-counting.
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