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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
Figure 19-14. CAN controller interrupt structure.
19.9.2
Interrupt behavior
When an interrupt occurs, an interrupt flag bit is set in the corresponding MOb-CANSTMOB register or in the gen-
eral CANGIT register. If in the CANIE register, ENRX / ENTX / ENERR bit are set, then the corresponding MOb bit
is set in the CANSITn register.
To acknowledge a MOb interrupt, the corresponding bits of CANSTMOB register (RXOK, TXOK,...) must be
cleared by the software application. This operation needs a read-modify-write software routine.
To acknowledge a general interrupt, the corresponding bits of CANGIT register (BXOK, BOFFIT,...) must be
cleared by the software application. This operation is made writing a logical one in these interrupt flags (writing a
logical zero doesn’t change the interrupt flag value).
OVRTIM interrupt flag is reset as the other interrupt sources of CANGIT register and is also reset entering in its
dedicated interrupt handler.
When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Conse-
quently, two consecutive interrupts can occur, both due to the same error.
When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in CANGIT register.
TXOK[i]
CANSTMOB.6
RXOK[i]
CANSTMOB.5
BERR[i]
CANSTMOB.4
SERR[i]
CANSTMOB.3
CERR[i]
CANSTMOB.2
FERR[i]
CANSTMOB.1
AERR[i]
CANSTMOB.0
BXOK
CANGIT.4
SERG
CANGIT.3
CERG
CANGIT.2
FERG
CANGIT.1
AERG
CANGIT.0
BOFFI
CANGIT.6
ENTX
CANGIE.4
ENRX
CANGIE.5
ENERR
CANGIE.3
ENBX
CANGIE.2
ENERG
CANGIE.1
ENBOFF
CANGIE.6
IEMOB[i]
CANIE 1/2
ENIT
CANGIE.7
ENOVRT
CANGIE.0
SIT[i]
CANSIT 1/2
CANIT
CANGIT.7
CAN IT
OVR IT
0
i
OVRTIM
CANGIT.5