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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
Table 17-12. Input mode operation.
17.16.10 PSC Interrupt Mask Register – PIM
Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 3 – PEVE2: PSC External Event 2 Interrupt Enable
When this bit is set, an external event which can generates a a fault on module 2 generates also an interrupt.
Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also an interrupt.
Bit 1 – PEVE: PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also an interrupt.
Bit 0 – PEOPE: PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
17.16.11 PIFR – PSC Interrupt Flag Register
Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 3 – PEV2: PSC External Event 2 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 2 occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE2 bit = 0).
PRFMn2:0
Description
000b
No action, PSC Input is ignored
001b
Disactivate module n Outputs A
010b
Disactivate module n Output B
011b
Disactivate module n Output A & B
10x
Disactivate all PSC Output
11xb
Halt PSC and wait for software action
Bit
7
654
3
2
1
0
-
PEVE2
PEVE1
PEVE0
PEOPE
PIM
Read/write
R
R/W
Initial value
0
Bit
7
654
3
2
1
0
-
PEV2
PEV1
PEV0
PEOP
PIFR
Read/write
R
R/W
Initial value
0