參數(shù)資料
型號: MR4A08ACYS35
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM
中文描述: 64K的x 16位的3.3V異步磁阻隨機存取內(nèi)存
文件頁數(shù): 7/20頁
文件大?。?/td> 148K
代理商: MR4A08ACYS35
Timing Specifications
MR0A16A Advanced Information Data Sheet, Rev. 0
Freescale Semiconductor
7
Timing Specifications
Read Mode
Table 9. Read Cycle Timing
1, 2
Parameter
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
BLQV
t
AXQX
t
ELQX
t
GLQX
t
BLQX
t
EHQZ
t
GHQZ
t
BHQZ
Min
35
3
3
0
0
0
0
0
Max
35
35
15
15
15
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address access time
Enable access time
3
Output enable access time
Byte enable access time
Output hold from address change
Enable low to output active
4, 5
Output enable low to output active
4, 5
Byte enable low to output active
4, 5
Enable high to output Hi-Z
4, 5
Output enable high to output Hi-Z
4, 5
Byte high to output Hi-Z
4, 5
NOTES:
1
W is high for read cycle.
Due to product sensitivities to noise, power supplies must be properly grounded and
decoupled, and bus contention conditions must be minimized or eliminated during read and
write cycles.
Addresses valid before or at the same time E goes low.
This parameter is sampled and not 100% tested.
Transition is measured
±
200 mV from steady-state voltage.
2
3
4
5
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