200
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
20.5.6.3
Handling LBT[5:0]
LDISR bit of LINBTR register is used to:
To enable the setting of LBT[5:0] (to manually adjust the baud rate especially in the case of UART mode). A
minimum of eight is required for LBT[5:0] due to the sampling operation
Disable the re-synchronization in LIN Slave Mode for test purposes
Note that the LENA bit of LINCR register is important for this handling (see
Figure 20-8).Figure 20-8. Handling LBT[5:0].
20.5.7
Data length
LTXDL[3..0] fields of LINDLR register before receiving or transmitting a response.
In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number of bytes already
successfully sent.
In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number of bytes already
successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
20.5.7.1
Data length in LIN 2.1
If LTXDL[3..0]=0 only the CHECKSUM will be sent
If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM
If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to eight after the command setting and before sending or
receiving of the first byte
20.5.7.2
Data length in LIN 1.3
LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code
contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL)
Via the above mechanism, a length of 0 or >8 is not possible
Write in LINBTR register
LENA ?
(LINCR bit 4)
LDISR
to write
=0
=1
LBT[5..0] forced to 0x20
LDISR forced to 0
Enable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
(LBT[5..0]min=8)
LDISR forced to 1
Disable re-synch. in LIN mode
=1