- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25640 > MQ80C52CXXX-30/883D (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44 PDF資料下載
參數(shù)資料
| 型號： | MQ80C52CXXX-30/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 60/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MQ80C52CXXX-30/883D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當(dāng)前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
260
XMEGA A [MANUAL]
8077I–AVR–11/2012
23.5.2 STATUS
– AES Status register
Bit 7
– ERROR: Error
The ERROR flag indicates an illegal handling of the AES crypto module. The flag is set in the following cases:
Setting START in the control register while the state memory and/or key memory are not fully loaded or read. This
error occurs when the total number of read/write operations from/to the STATE and KEY registers is not a multiple
of 16 before an AES start.
Accessing (read or write) the control register while the START bit is one.
This flag can be cleared by software by writing one to its bit location.
Bit 6:1
– Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 0
– SRIF: State Ready Interrupt flag
This flag is the interrupt/DMA request flag, and is set when the encryption/decryption procedure is completed and the
state memory contains valid data. As long as the flag is zero, this indicates that there is no valid encrypted/decrypted
data in the state memory.
The flag is cleared by hardware when a read access is made to the state memory (the first byte is read). Alternatively, the
bit can be cleared by writing a one to its bit location.
23.5.3 STATE
– AES State register
The STATE register is used to access the state memory. Before encryption/decryption can take place, the state memory
must be written sequentially, byte-by-byte, through the STATE register. After encryption/decryption is done, the
ciphertext/plaintext can be read sequentially, byte-by-byte, through the STATE register.
Loading the initial data to the STATE register should be done after setting the appropriate AES mode and direction. This
register can not be accessed during encryption/decryption.
23.5.4 KEY
– Key register
The KEY register is used to access the key memory. Before encryption/decryption can take place, the key memory must
be written sequentially, byte-by-byte, through the KEY register. After encryption/decryption is done, the last subkey can
be read sequentially, byte-by-byte, through the KEY register. Loading the initial data to the KEY register should be done
after setting the appropriate AES mode and direction.
Bit
765
432
10
+0x01
ERROR
–
–SRIF
Read/Write
R/W
R
R/W
Initial Value
000
00
Bit
765
43
210
+0x02
STATE[7:0]
Read/Write
R/W
Initial Value
000
00
000
Bit
7654
3210
+0x03
KEY[7:0]
Read/Write
R/W
Initial Value
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C32E-36/883D | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C154-25/883 | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| MSP430F2003TRSAR | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC16 |
| MSP430F2012IRSAR | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC16 |
| MSP430F2013TRSAR | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ82370-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ8238020 | 制造商:Intel 功能描述:CONTROLLER: OTHER |
| MQ82380-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ82380-20/R | 制造商:Rochester Electronics LLC 功能描述: |
| MQ82592 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。