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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-30/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 29/80頁(yè) |
| 文件大?。?/td> | 5152K |
| 代理商： | MQ80C52CXXX-30/883D |
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220
2466T–AVR–07/10
ATmega16(L)
The ADC Data
Register – ADCL and
ADCH
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
Table 85. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
00
0
2
00
1
2
01
0
4
01
1
8
10
0
16
10
1
32
11
0
64
1
128
Bit
151413121110
9
8
–
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
765
4321
0
Read/Write
RRRR
Initial Value
000
0000
0
000
0000
0
Bit
1514131211
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
–
––––
–
ADCL
765
4321
0
Read/Write
RRRR
Initial Value
000
0000
0
000
0000
0
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