777
32099I–01/2012
AT32UC3L016/32/64
Notes:
1. V
VDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2 on page 9 for details. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
VIL
Input low-level voltage
V
VDD = 3.0 V
-0.3
0.3*V
VDD
V
VDD = 1.62 V
-0.3
0.3*V
VDD
VIH
Input high-level voltage
VVDD = 3.6V
0.7*VVDD
VVDD + 0.3
V
VDD = 1.98V
0.7*V
VDD
V
VDD + 0.3
V
OL
Output low-level voltage
VVDD = 3.0V, IOL = 6mA
0.4
V
VVDD = 1.62V, IOL = 4mA
0.4
VOH
Output high-level voltage
V
VDD = 3.0 V, IOH = 6 mA
V
VDD-0.4
V
VVDD = 1.62V, IOH = 4mA
VVDD-0.4
f
MAX
Output frequency, all High-
drive I/O pins, except
VVDD = 3.0V, load = 10pF
45
MHz
VVDD = 3.0V, load = 30pF
23
t
RISE
Rise time, all High-drive
I/O pins, except PA08 and
VVDD = 3.0V, load = 10pF
4.7
ns
VVDD = 3.0V, load = 30pF
11.5
t
FALL
Fall time, all High-drive I/O
pins, except PA08 and
VVDD = 3.0V, load = 10pF
4.8
VVDD = 3.0V, load = 30pF
12
fMAX
Output frequency, PA08
VVDD = 3.0V, load = 10pF
52
MHz
V
VDD = 3.0 V, load = 30 pF
39
t
RISE
Rise time, PA08 and
VVDD = 3.0V, load = 10pF
2.9
ns
V
VDD = 3.0 V, load = 30 pF
4.9
t
FALL
Fall time, PA08 and
V
VDD = 3.0 V, load = 10 pF
2.5
VVDD = 3.0V, load = 30pF
4.6
I
LEAK
Input leakage current
Pull-up resistors disabled
1
A
CIN
Input capacitance, all
High-drive I/O pins, except
PA08 and PA09
TQFP48 package
2,2
pF
QFN48 package
2.0
TLLGA 48 package
2.0
CIN
Input capacitance, PA08
and PA09
TQFP48 package
7.0
QFN48 package
6.7
TLLGA 48 package
6.7
Table 32-8.
High-drive I/O Pin Characteristics
(1)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Table 32-9.
High-drive I/O, 5V Tolerant, Pin Characteristics
(1)Symbol
Parameter
Condition
Min
Typ
Max
Units
RPULLUP
Pull-up resistance
30
50
110
kOhm
VIL
Input low-level voltage
VVDD = 3.0V
-0.3
0.3*VVDD
V
VDD = 1.62 V
-0.3
0.3*V
VDD