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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67717 > MQ80C52CXXX-25P883R (ATMEL CORP) 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 PDF資料下載

型號(hào)：	MQ80C52CXXX-25P883R
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	335/849頁(yè)
文件大?。?/td>	12530K
代理商：	MQ80C52CXXX-25P883R

32099I–01/2012

AT32UC3L016/32/64

Power-up Sequence

Maximum Rise Rate

To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values

Recommended order for power supplies is also described in this chapter.

Minimum Rise Rate

The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply

requires a minimum rise rate for the VDDIN power supply.

See Table 32-3 on page 771 for the minimum rise rate value.

If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-

ply is met, one of the following configurations can be used:

A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V.

A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.

Startup Considerations

This chapter summarizes the boot sequence of the AT32UC3L016/32/64. The behavior after

power-up is controlled by the Power Manager. For specific details, refer to the Power Manager

Starting of Clocks

After power-up, the device will be held in a reset state by the Power-on Reset (POR18 and

POR33) circuitry for a short time to allow the power to stabilize throughout the device. After

reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to

Table 32-17 on page 783 for the frequency for this oscillator.

On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have

a divided frequency; all parts of the system receive a clock with the same frequency as the Sys-

tem RC Oscillator.

When powering up the device, there may be a delay before the voltage has stabilized, depend-

ing on the rise time of the supply used. The CPU can start executing code as soon as the supply

is above the POR18 and POR33 thresholds, and before the supply is stable. Before switching to

a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above

the minimum level (1.62V).

Fetching of Initial Instructions

After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset

address, which is 0x80000000. This address points to the first address in the internal flash.

The code read from the internal flash is free to configure the clock system and clock sources .

Please refer to the Power Manager and SCIF chapters for details.

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MQ82380-20/R	制造商:Rochester Electronics LLC 功能描述:
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