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參數(shù)資料
| 型號： | MPC961CFA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 159K |
| 代理商： | MPC961CFA |
MPC961C
488
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
seen looking into the driver. The parallel combination of the 36
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS (ZO / (RS + RO +ZO))
ZO = 50 || 50
RS = 36 || 36
RO = 14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31 V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.62 V. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 6 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
Figure 6. Optimized Dual Line Termination
SPICE level and IBIS output buffer models are available for
engineers who want to simulate their specific interconnect
schemes.
Using the MPC961C in Zero-Delay Applications
Nested clock trees are typical applications for the MPC961C.
Designs using the MPC961C as LVCMOS PLL fanout buffer
with zero insertion delay will show significantly lower clock skew
than clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC961C clock driver
allows for its use as a zero delay buffer. By using the QFB
output as a feedback to the PLL the propagation delay through
the device is virtually eliminated. The PLL aligns the feedback
clock output edge with the clock input reference edge resulting
a near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This effective
delay consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC961C zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961C are connected together, the maximum overall timing
uncertainty from the common CCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 7. MPC961C Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter a rms value (1
σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.Confidence Factor CF.
TIME (ns)
VOLT
AGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC961
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MPC961PAC | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC961PACR2 | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC961PFA | 功能描述:IC ZDB PECL LV 1:18 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC962305 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305D-1 | 功能描述:IC CLOCK BUFFER 1:5 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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