- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369928 > MPC954 (Motorola, Inc.) Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC954 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器（低壓鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 96K |
| 代理商： | MPC954 |
MPC954
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
4
Power Supply Filtering
The MPC954 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC954 provides separate
power supplies for the output buffers (VCCO) and the
phase–locked loop (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC954.
Figure 3 illustrates a typical power supply filter scheme.
The MPC954 is most susceptible to noise with spectral
content in the 1KHz to 10MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC954. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15
to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
with an 8–10
resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
Figure 3. Power Supply Filter
VCCA
VCC
MPC954
0.01
μ
F
22
μ
F
0.01
μ
F
3.3V
RS=5–15
Although the MPC954 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Driving Transmission Lines
The MPC954 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC954 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC954 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 4. Single versus Dual Transmission Lines
7
IN
MPC954
OUTPUT
BUFFER
RS = 43
ZO = 50
OutA
7
IN
MPC954
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC954 output buffers is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC954. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC961 | Low Voltage Zero Delay Buffer(低壓零延遲緩沖器) |
| MPX2000 | Pressure Sensor(壓力傳感器) |
| MPX2010 | Pressure Sensor(壓力傳感器) |
| MPX2053 | 50 KPA ON CHIP TEMPERATURE COMPENSATED CALIBRATED SILICON PRESSURE SENSORS |
| MPXV2053DP | 50 KPA ON CHIP TEMPERATURE COMPENSATED CALIBRATED SILICON PRESSURE SENSORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC958 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9600 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| MPC9600AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9600AER2 | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9600FA | 功能描述:IC CLOCK DRVR PLL LV 1:21 48LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。