參數(shù)資料
型號(hào): MPC954
廠商: Motorola, Inc.
英文描述: Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器)
中文描述: 低電壓PLL時(shí)鐘驅(qū)動(dòng)器(低壓鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器)
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 96K
代理商: MPC954
SEMICONDUCTOR TECHNICAL DATA
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REV 0
Motorola, Inc. 1998
11/98
The MPC954 is a 3.3V compatible, PLL based zero delay buffer
targeted for high performance clock tree designs. With 11 outputs at
frequencies of up to 125MHz and output skews of 200ps the MPC954 is
ideal for the most demanding clock tree designs. The devices employ a
fully differential PLL design to minimize cycle–to–cycle and phase jitter.
Fully Integrated PLL
Output Frequency up to 125MHz in PLL Mode
Outputs Disable in High Impedance
TQFP Packaging
50ps Cycle–to–Cycle Jitter
The analog VCC pin of the device also serves as a PLL bypass select
pin. When driven low the AVCC pin will route the REF_CLK input around
the PLL directly to the outputs. The OE input is a logic enable for all of the
outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low
state.
The MPC954 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50
transmission lines. The output impedance
of the MPC954 is
10 , therefore for series terminated 50
lines, each
of the MPC954 outputs can drive two traces giving the device an effective
fanout of 1:22. The device is packaged in a 24–lead TSSOP package to
provide the optimum combination of board density and performance.
Figure 1. Block Diagram
REF_CLK
FB_CLK
PLL
AVCC
Q0
Q9
QFB
OE
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW VOLTAGE
PLL ZERO DELAY BUFFER
DT SUFFIX
24–LEAD TSSOP PACKAGE
CASE 948H–01
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