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參數(shù)資料
| 型號(hào)： | MPC961 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage Zero Delay Buffer(低壓零延遲緩沖器) |
| 中文描述： | 低壓零延遲緩沖器（低壓零延遲緩沖器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 115K |
| 代理商： | MPC961 |
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC961/D
1
REV 0
Motorola, Inc. 1999
01/99
The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay
buffer. With output frequencies of up to 200MHz, output skews of 150ps
and part–to–part skews of 500ps the device meets the needs of the most
demanding clock tree applications.
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVCMOS or LVPECL Reference Clock Options
QFP Packaging
±
50ps Cycle–Cycle Jitter
150ps Output Skews
500ps Part–to–Part Skews
The MPC961 is offered with two different input configurations. The
MPC961C offers an LVCMOS reference clock while the MPC961P offers
an LVPECL reference clock. The LVPECL reference clock feature allows
the designer to use LVPECL fanout buffers for the inner branches of the
clock distribution tree. LVPECL fanout buffers offer a significant skew
performance boost over LVCMOS alternatives.
The VCCA analog power pin doubles as a PLL bypass select line.
When the VCCA pin is driven to ground the reference clock will bypass the
PLL and will drive the outputs directly. When pulled high the OE pin will
force all of the outputs (except QFB) into a high impedance state.
Because the OE pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept
LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50
transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of
1:36. The device is packaged in a 32 lead QFP package to provide the optimum combination of board density and performance.
Figure 1. Logic Diagram
PCLK
PCLK
FB_IN
PLL
Q0
Q16
QFB
CCLK
F_RANGE
VCCA
OE
MPC961C
MPC961P
O
I
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW VOLTAGE
ZERO DELAY BUFFER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC961C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE ZERO DELAY BUFFER |
| MPC961CAC | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC961CACR2 | 功能描述:IC BUFFER ZD 1:18 PLL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC961CFA | 功能描述:IC ZDB CMOS LV 1:18 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC961PAC | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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