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參數資料
| 型號： | MPC951FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 951 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數： | 8/10頁 |
| 文件大小： | 336K |
| 代理商： | MPC951FA |
MPC951
TIMING SOLUTIONS
BR1333 — Rev 6
7
MOTOROLA
Two different configurations were chosen to look at the
period displacement caused by the switching outputs.
Configuration 3 is considered worst case as the “trimodal”
distribution (as pictured in Figure 3) represents the largest
spread between distribution peaks. Configuration 2 is
considered a typical configuration with half the outputs at a
high frequency and the remaining outputs at one half the high
frequency. For these cases the peak–to–peak numbers are
reported in Figure 5 as the sigma numbers are useless
because the distributions are not Gaussian. For situations
where the outputs are synchronous and switching at different
frequencies the measurement technique described here is
insufficient to use for establishing guaranteed limits. Other
techniques are currently being investigated to identify a more
accurate and repeatable measurement so that guaranteed
limits can be provided. The data generated does give a good
indication of the general performance, a performance that in
most cases is well within the requirements of today’s
microprocessors.
Finally from the data there are some general guidelines
that, if followed, will minimize the output jitter of the device.
First and foremost always configure the device such that the
VCO runs as fast as possible. This is by far the most critical
parameter in minimizing jitter. Second keep the reference
frequency as high as possible. More frequent updates at the
phase detector will help to reduce jitter. Note that if there is a
tradeoff between higher reference frequencies and higher
VCO frequency always chose the higher VCO frequency to
minimize jitter. The third guideline may be the most difficult,
and in some cases impossible, to follow. Try to minimize the
number of different frequencies sourced from a single chip.
The fixed edge displacement associated with the switching
noise in most cases nearly doubles the “effective” jitter of a
high speed output.
Power Supply Filtering
The MPC951 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC951 provides separate
power supplies for the output buffers (VCCO) and the
phase–locked loop (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC951.
Figure 6 illustrates a typical power supply filter scheme.
The MPC951 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC951. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 6 must have a resistance of 10–15
to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
with an 8–10
resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
Figure 6. Power Supply Filter
VCCA
VCC
MPC951
0.01
F
22
F
0.01
F
3.3V
RS=5–15
Although the MPC951 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Driving Transmission Lines
The MPC951 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC951 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
MPC951
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC951
7
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