參數(shù)資料
型號(hào): MPC8572VTAVLD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 124/138頁
文件大?。?/td> 1502K
代理商: MPC8572VTAVLD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
86
Freescale Semiconductor
PCI Express
16.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 55 is specified using the passive compliance/test measurement load (see
Figure 57) in place of any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (i.e., least squares and median deviation fits).
Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications
相關(guān)PDF資料
PDF描述
MPC8572CVTAULD 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
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