參數(shù)資料
型號： MPC8572VTAVLD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝： 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 118/138頁
文件大?。?/td> 1502K
代理商： MPC8572VTAVLD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
80
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 51 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with MPC8572E SerDes reference clock
input’s DC requirement.
Figure 51. Single-Ended Connection (Reference Only)
15.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 57 describes some AC parameters common to SGMII, PCI Express and Serial RapidIO protocols.
Table 57. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
2, 3
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
2, 3
Differential Input High Voltage
VIH
+200
mV
2
Differential Input Low Voltage
VIL
—-200
mV
2
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
MPC8572E
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
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