參數(shù)資料
型號： MPC8572CVTAVNE
廠商： Freescale Semiconductor
文件頁數(shù)： 68/138頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
35
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 12 shows the MII transmit AC timing diagram.
Figure 12. MII Transmit AC Timing Diagram
8.2.3.2
MII Receive AC Timing Specifications
Table 30 provides the MII receive AC timing specifications.
Figure 13 provides the AC test load for eTSEC.
Figure 13. eTSEC AC Test Load
Table 30. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
2
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—40
—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
ns
RX_CLK clock rise (20%-80%)
tMRXR
2
1.0
—
4.0
ns
RX_CLK clock fall time (80%-20%)
tMRXF
2
1.0
—
4.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
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