參數(shù)資料
型號： MPC8572CVTAVNE
廠商： Freescale Semiconductor
文件頁數(shù)： 115/138頁
文件大小： 0K
描述： MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
78
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 49 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Because LVDS clock driver’s common mode voltage is higher than the MPC8572E SerDes reference
clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Figure 49. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 50 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Because LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible
with MPC8572E SerDes reference clock input’s DC requirement, AC-coupling must be used. Figure 50
assumes that the LVPECL clock driver’s output impedance is 50
Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140
Ω to 240Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8572E SerDes
reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).
For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock
input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25
Ω. Consult
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8572E
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