參數(shù)資料
型號： MPC8572CVTAVNE
廠商： Freescale Semiconductor
文件頁數(shù)： 22/138頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
118
Freescale Semiconductor
Clocking
As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following
procedures can be used:
Start with the processor core frequency selection;
After the processor core frequency is determined, select the platform (CCB) frequency from the
limited options listed in Table 80 and Table 81;
Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from Table 79;
If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;
Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR
data rate to DDRCLK ratio from Table 82. Note that in asynchronous mode, the DDR data rate
must be greater than the platform (CCB) frequency. In other words, running DDR data rate lower
than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
19.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in Table 79:
SYSCLK input signal
Binary value on LA[29:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,
because the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock
frequency is decoupled from the CCB bus frequency.
19.3
e500 Core PLL Ratio
The clock speed for each e500 core can be configured differently, determined by the values of various
signals at power up.
Table 79. CCB Clock Ratio
Binary Value of
LA[29:31] Signals
CCB:SYSCLK Ratio
000
4:1
001
5:1
010
6:1
011
8:1
100
10:1
101
12:1
110
Reserved
111
Reserved
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