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| 型號(hào)： | MPC8572CLVTAULE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 94/138頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤(pán) |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
59
Local Bus Controller (eLBC)
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of tLBKHKT. In this mode, signals are launched at the rising edge
of the internal clock and are captured at the falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
LALE output negation to high impedance for
LAD/LDP (LATCH hold time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and
LALE)
tLBKLOV1
—–0.3
ns
Local bus clock to data valid for LAD/LDP
tLBKLOV2
—–0.1
ns
4
Local bus clock to address valid for LAD
tLBKLOV3
—0.0
ns
4
Local bus clock to LALE assertion
tLBKLOV4
—0.0
ns
4
Output hold from local bus clock (except LAD/LDP
and LALE)
tLBKLOX1
–3.3
—
ns
4
Output hold from local bus clock for LAD/LDP
tLBKLOX2
–3.3
—
ns
4
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKLOZ1
—0.2
ns
7
Local bus clock to output high impedance for
LAD/LDP
tLBKLOZ2
—0.2
ns
7
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by tLBKHKT.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is
programmed with the LBCR[AHD] parameter.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
Table 52. Local Bus General Timing Parameters—PLL Bypassed (continued)
At recommended operating conditions with BVDD of 3.3 V ± 5%
Parameter
Symbol 1
Min
Max
Unit
Notes
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