參數(shù)資料
型號： MPC8572CLVTAULE
廠商： Freescale Semiconductor
文件頁數(shù)： 130/138頁
文件大小： 0K
描述： MPU POWERQUICC III 1023FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
91
Serial RapidIO
17.5
Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case shall be better than
–10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and
–10 dB + 10log(f/625 MHz) dB for 625 MHz
≤ Freq(f) ≤ Baud Frequency
The reference impedance for the differential return loss measurements is 100
Ω resistive. Differential
return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components
related to the driver. The output impedance requirement applies to all valid output levels.
It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output,
in each case have a minimum value 60 ps.
It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals
that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.
Table 65. Short Run Transmitter AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
500
1000
mV p-p
—
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—
0.35
UI p-p
—
Multiple output skew
SMO
—
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
800
ps
+/- 100 ppm
Table 66. Short Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
500
1000
mV p-p
—
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—
0.35
UI p-p
—
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