參數(shù)資料
型號： MPC8569VTAUNLA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 99/126頁
文件大小： 2847K
代理商： MPC8569VTAUNLA
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Ethernet Management Interface
Freescale Semiconductor
74
2.7.1.1
MII Management AC Electrical Specifications
The following table provides the MII management AC timing specifications.
Input low current (LVDD = Max, VIN = 0.5 V)
IIL
–600
—
μA1
Output high voltage (LVDD = Min, IOH = –4.0 mA)
VOH
2.4
—
V
—
Output low voltage (LVDD = Min, IOL = 4.0 mA)
VOL
—0.4
V
—
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3.
Table 42. MII Management AC Timing Specifications
At recommended operating conditions with LVDD = 3.3 V ± 5%.
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
2
MDC period
tMDC
—400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
ns
—
MDC to MDIO valid
tMDKHDV
2
× (tplb_clk*8)
—
ns
4
MDC to MDIO delay
tMDKHDX
(16
× tplb_clk) – 3
—
(16
× tplb_clk) + 3
ns
3, 4, 5
MDIO to MDC setup time
tMDDVKH
10
—
ns
—
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
—
10
ns
—
MDC fall time
tMDCF
—
10
ns
—
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reaching the valid
state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
the Mgmt Clock CE_MDC).
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
example, with a platform clock of 400 MHz, the min/max delay is 40 ns ± 3 ns.
4. tplb_clk is the QUICC Engine block clock/2.
5. MDC to MDIO Data valid tMDKHDV is a function of clock period and max delay time (tMDKHDX).
(Min setup = cycle time – max delay
Table 41. MII Management DC Electrical Characteristics (continued)
At recommended operating conditions with LVDD = 3.3 V
Parameter
Symbol
Min
Max
Unit
Notes
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