參數(shù)資料
型號: MPC8569VTAUNLA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 93/126頁
文件大?。?/td> 2847K
代理商: MPC8569VTAUNLA
Ethernet Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
69
2.6.4.1.3
SGMII DC Receiver Electrical Characteristics
The following table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock
is recovered from the data.
s
2.6.4.2
SGMII AC Timing Specifications
This section discusses the AC timing specifications for the SGMII interface.
2.6.4.2.1
AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
Note that the SGMII clock requirements for SD_REF_CLK and SD_REF_CLK are intended to be used within the clocking
Table 37. SGMII DC Receiver Electrical Characteristics
At recommended operating conditions with XVDD = 1.0 V ± 3% and 1.1 V ± 3%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
DC Input voltage range
N/A
1
Input differential voltage
LSTS = 001
VRX_DIFFp-p
100
1200
mV
2, 4
LSTS = 100
175
Loss of signal threshold
LSTS = 001
VLOS
30
100
mV
3, 4
LSTS = 100
65
175
Receiver differential input impedance
ZRX_DIFF
80
120
Ω
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See
Specifications,” for further explanation.
4. The LSTS shown in this table refers to the LSTS2 or LSTS3 bit field of the MPC8569E‘s SerDes control register SRDSCR4.
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