參數(shù)資料
型號(hào)： MPC8569EVTAUNL
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 95/126頁
文件大?。?/td> 2847K
代理商： MPC8569EVTAUNL
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Ethernet Interface
Freescale Semiconductor
70
2.6.4.2.2
SGMII Transmit AC Timing Specifications
The following table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The
AC timing specifications do not include RefClk jitter.
2.6.4.2.3
SGMII AC Measurement Details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) or at the receiver
inputs (SD_RXn and SD_RXn), as depicted in the following figure, respectively.
Figure 29. SGMII AC Test/Measurement Load
2.6.4.2.4
SGMII Receiver AC Timing Specifications
The following table provides the SGMII receive AC timing specifications. The AC timing specifications do not include RefClk
jitter. Source synchronous clocking is not supported. Clock is recovered from the data.
Table 38. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XVDD = 1.0 V ± 3% and 1.1 V ± 3%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic jitter
JD
—
0.17
UI p-p
—
Total jitter
JT
—
0.35
UI p-p
2
Unit interval
UI
799.92
800
800.08
ps
1
AC coupling capacitor
CTX
75
100
200
nF
3
Notes:
1. Each UI is 800 ps ± 100 ppm.
2. See Figure 30 for single frequency sinusoidal jitter limits.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
Table 39. SGMII Receive AC Timing Specifications
At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
1, 2, 4
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
—
UI p-p
1, 2, 4
TX
Silicon
+ Package
C = CTX
R = 50
Ω
R = 50
Ω
D+ Package
Pin
D– Package
Pin
D+ Package
Pin
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