參數(shù)資料
型號： MPC8569EVTAUNL
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 57/126頁
文件大小： 2847K
代理商： MPC8569EVTAUNL
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Overall DC Electrical Characteristics
Freescale Semiconductor
36
2
Electrical Characteristics
This section provides the AC and DC electrical specifications for the MPC8569E. This device is currently targeted to these
specifications, some of which are independent of the I/O cell, but are included for a more complete reference. These are not
purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the DC ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
The following table provides the absolute maximum ratings.
26. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
27. When operating in DDR2 mode, connect Dn_MDIC[0] to ground through an 18.2-
Ω (full-strength mode) or 36.4-Ω
(half-strength mode) precision 1% resistor and connect Dn_MDIC[1] to GVDD through an 18.2-Ω (full-strength mode) or
36.4-
Ω (half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect Dn_MDIC[0] to ground through
a 20-
Ω (full-strength mode) or 40.2-Ω (half-strength mode) precision 1% resistor and connect Dn_MDIC[1] to GVDD through
a 20-
Ω(full-strength mode) or 40.2-Ω(half-strength mode) precision 1% resistor. These pins are used for automatic calibration
of the DDR IOs.
28. Recommend a pull-up resistor (1 k
Ω) to be placed on this pin to OVDD.
29. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pull up on LGPL4
is required.
30. If unused, these pins must be connected to GND.
31. If unused, these pins must be left unconnected.
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Range
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.21
V
—
PLL supply voltage
AVDD_CORE
AVDD_DDR,
AVDD_LBIU,
AVDD_PLAT,
AVDD_QE,
AVDD_SRDS
–0.3 to 1.21
V
—
Core power supply for SerDes transceiver
ScoreVDD
–0.3 to 1.21
V
—
Pad power supply for SerDes transceiver
XVDD
–0.3 to 1.21
V
—
DDR2 and DDR3 DRAM I/O voltage
GVDD
–0.3 to 1.98
–0.3 to 1.65
V2
QUICC Engine block Ethernet interface I/O voltage
LVDD1
–0.3 to 3.63
–0.3 to 2.75
V—
QUICC Engine block Ethernet interface I/O voltage
LVDD2
–0.3 to 3.63
–0.3 to 2.75
V—
Table 1. MPC8569E Pinout Listing (continued)
Signal1
Package Pin Number
Pin Type
Power Supply
Note
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MPC8569EVTAUNLB 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 1.33GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569VJAUNLB 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 1333MHZ 783FCBGA
MPC8569VTANKGB 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 800/600/400 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569VTAQLJB 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569VTAUNLB 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1333/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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