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參數(shù)資料
| 型號： | MPC8569EVTAUNL |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 56/126頁 |
| 文件大?。?/td> | 2847K |
| 代理商： | MPC8569EVTAUNL |
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Pinout List
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
35
XGND
W23
SerDes Transceiver
Pad GND
——
XGND
Y21
SerDes Transceiver
Pad GND
——
AGND_SRDS
U25
SerDes PLL GND
—
Notes:
1. All multiplexed signals are listed only once and do not reoccur.
2. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ωpull-down resistor. However, if the
signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at
reset, then a pull-up or active driver is needed.
3. When configured as I2C, this pin is an open drain signal and recommend a pull-up resistor (1 k
Ω) be placed on this pin to
OVDD. When configured as SD, this pin is not open drain and does not require a pull-up.
4. This pin has a weak internal pull-up resistor (~20 k
Ω).
5. This pin is an open drain signal.
6. Recommend a weak pull-up resistor (2–10 k
Ω) be placed on this pin to OVDD.
7. This pin requires a 200-
Ω pull-down to ground.
8. Do not connect.
9. Recommend a weak pull-down resistor (2–10 k
Ω) be placed on this pin to GND.
10. These are test signals for factory use only and must be pulled up (100
Ω–1 kΩ) to OVDD for normal machine operation.
11. These pins must not be pulled down during power-on reset.
12. See AN4232 MPC8569E PowerQUICC III Design Checklist for the required PLL filters to be attached to the AVDD pin.
13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14. This pin selects the voltage of eLBC interface (BVDD). This pin has internal weak pull down.
15. This pin selects the voltage of UCC1 and UCC3 interfaces (LVDD1). This pin has internal weak pull down.
16. This pin selects the voltage of UCC2 and UCC4 interfaces (LVDD2). This pin has internal weak pull down.
17. This pin requires a 100-
Ω pull down to ground.
18. The value of LA[24:27] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ωpull-up or pull-down
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
19. The value of QE_PE[27:29] during reset sets the DDR clock PLL settings. These pins require 4.7-k
Ω pull up or pull down
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
20. The value of LALE, LGPL2/LOE/LFRE and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins
require 4.7-k
Ωpull-up or pull-down resistors. See the AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
21. The value of LCS[3:7] at reset sets the QE PLL settings. These pins require 4.7-k
Ω pull up or pull down resistors. See
AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
22. The value of QE_PB[27:28], QE_PC4 and QE_PD4 at reset sets the Boot ROM location. These pins require 4.7-k
Ω pull up
or pull down resistors. See the MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual for details
23. These pins are sampled at reset for general-purpose configuration use by software. The value of LAD[0:15] at reset sets the
upper 16 bits of the GPPORCR
24. These pins must not be pulled up during power-on reset.
25. This output is actively driven during reset rather than being three-stated during reset.
Table 1. MPC8569E Pinout Listing (continued)
Signal1
Package Pin Number
Pin Type
Power Supply
Note
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8569EVTAUNLB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 1.33GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VJAUNLB | 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 1333MHZ 783FCBGA |
| MPC8569VTANKGB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 800/600/400 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VTAQLJB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VTAUNLB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1333/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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