參數(shù)資料
型號： MPC8568ECVTAQGGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 93/139頁
文件大?。?/td> 1449K
代理商： MPC8568ECVTAQGGA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
57
I
2C
11.2
I2C AC Electrical Specifications
Table 47 provides the AC timing parameters for the I2C interfaces.
Capacitance for each I/O pin
CI
—10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the MPC8568E PowerQUICC III Integrated Communications Processor Reference Manual for information on the
digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 47. I2C AC Electrical Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
ns
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0 2
—
μs
Data output delay time
tI2OVKL
—0.9 3
μs
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Table 46. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit Notes
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