參數(shù)資料
型號： MPC8568ECVTAQGGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 62/139頁
文件大?。?/td> 1449K
代理商： MPC8568ECVTAQGGA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
29
Ethernet Interface and MII Management
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see Section
4.4, “Platform to FIFO restrictions.
A summary of the FIFO AC specifications appears in Table 25 and Table 26.
Table 25. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period
tFIT
5.0
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
—
250
ps
Rise time TX_CLK (20%–80%)
tFITR
—0.75
1.5
ns
Fall time TX_CLK (80%–20%)
tFITF
—0.75
1.5
ns
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
tFITDV
2.0
—
ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
tFITDX
0.5 1
—3.0
ns
Table 26. FIFO Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
tFIR
5.0
8.0
100
ns
RX_CLK duty cycle
tFIRH/tFIRH
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
——
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
—0.75
1.5
ns
Fall time RX_CLK (80%–20%)
tFIRF
—0.75
1.5
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
—
ns
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